Physical Design Engineer

Company: Tanisha Systems
Location: Sunnyvale
Posted on: April 2, 2025

Job Description:

Role: Physical Design Engineer

Do not pass up this chance, apply quickly if your experience and skills match what is in the following description.
Location: Sunnyvale CA
Type: preferred Fulltime

Required Experience Range: 05 to 15 years

Job Description:
We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning.


Key Responsibilities:

Block-Level Physical Design: Floor planning & Partitioning - Define optimal floorplan with power grid, macro placements, and congestion analysis.
Strong scripting experience.
Placement & Optimization - Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
Clock Tree Synthesis (CTS) - Design and optimize low-skew, high-performance clock networks.
Routing & DRC Closure - Ensure successful global and detailed routing, meeting design rule constraints.
Timing Closure - Work on setup/hold timing violations, signal integrity, and crosstalk reduction using static timing analysis (STA).
Power & IR Drop Analysis - Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.


Top-Level Physical Design: Chip-Level Floor planning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations.
Strong scripting experience.
Clock & Power Distribution - Design robust clock trees and power delivery networks (PDN).
Integration of IP & Sub-blocks - Ensure seamless integration of IP blocks and handle complex routing challenges.
Chip Assembly & Sign-Off - Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
DFT Integration - Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.


About Tanisha Systems, Inc.

Tanisha Systems, founded in 2002 in Massachusetts-*, is a leading provider of Custom Application Development and end-to-end IT Services to clients globally. We use a client-centric engagement model that combines local on-site and off-site resources with the cost, global expertise and quality advantages of off-shore operations. We deliver Custom Application Development, Application Modernization, Business Process Outsourcing and Professional IT Services from office locations in * and *.
Tanisha Systems services clients in Government, Banking & Financial Markets, Insurance, Healthcare, Retail & Consumer Goods, Energy & Utilities, Life Sciences, Telecom, Manufacturing and Transportation Industries around the globe. Our engagement model provides a flexible operational environment that empowers our clients with the right levels of control.

Want to read more about Tanisha Systems? Visit us at www.tanishasystems.com

Website Open Jobs

Keywords: Tanisha Systems, Sunnyvale , Physical Design Engineer, Engineering , Sunnyvale, California